AMD SB7xxx: bit2 is trigger, bit1 and bit3 considered bit1 - send HT INIT if 0 if 1 then bit3 bit3 - 0 assert resets, 1 put system to S5 for few seconds
VIA has a similar mechanism, bit2 is reset trigger, bit1 selects a PCIRST or INIT.
Look to sources in coreboot.org for the hard_reset and soft reset sequences.
I think those two phase settings is because PIIX4 had some bug, where there had to be a transition. New chipsets seems to require just only one write.
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cf9 resets
Date: 2011-06-01 12:56 pm (UTC)AMD SB7xxx:
bit2 is trigger, bit1 and bit3 considered
bit1 - send HT INIT if 0 if 1 then bit3
bit3 - 0 assert resets, 1 put system to S5 for few seconds
VIA has a similar mechanism, bit2 is reset trigger, bit1 selects a PCIRST or INIT.
Look to sources in coreboot.org for the hard_reset and soft reset sequences.
I think those two phase settings is because PIIX4 had some bug, where there had to be a transition. New chipsets seems to require just only one write.